#This is the microcode for our bus controller
#Mux data:
#	000-RR
#	001->butt
#	010->Switch
#	011->Z
#	100->Zero (0)
#	101->Switch 2
#
#                /RD   ADC1
#                | /CS ADC1
#                | | /RD   ADC2  
#                | | | /CS ADC2
#                | | | | Count 
#                | | | | | /CS       DAC
#                | | | | | | /WR     DAC
#                | | | | | | | /LDAC DAC
#                | | | | | | | | /WE     RAM
#                | | | | | | | | | /OE   RAM
#                | | | | | | | | | | /CE RAM
#                | | | | | | | | | | | GREEN 
#         p      | | | | | | | | | | | | RED
#Cur. MUX o next | | | | | | | | | | | | | CLR
#stat sel l stat | | | | | | | | | | | | | |

 AAAA 000 0 0000 2 2 2 2 1 2 2 2 1 1 1 1 1 1

 0000 101 1 1100 1 1 1 1 0 1 1 1 1 1 1 1 1 0
 0001 001 0 0000 1 1 1 1 0 1 1 1 1 1 1 1 1 0
 0010 100 1 0011 0 0 1 1 0 1 1 1 1 1 1 1 0 1
 0011 000 1 0110 0 0 1 1 1 1 1 1 0 1 0 1 0 1
 0100 100 0 0010 1 0 1 1 0 1 1 1 1 1 1 1 0 1
 0110 010 0 0110 1 1 1 1 0 1 1 1 1 1 1 1 1 0
 0111 100 1 1000 1 1 1 1 0 1 1 1 1 0 0 0 1 1
 1000 010 0 0110 1 1 1 1 1 0 0 1 1 0 0 0 1 1
 1001 011 0 0111 1 1 1 0 0 1 0 0 1 1 1 0 1 1
 1010 100 0 0101 1 1 0 0 0 1 1 1 1 1 1 0 1 1
 0101 010 1 1001 1 1 0 0 1 0 0 1 1 1 1 0 1 1
 1100 011 1 1110 1 1 1 1 0 1 0 0 1 1 1 0 1 1
 1101 100 0 1011 0 0 1 1 0 1 1 1 1 1 1 0 1 1
 1011 101 0 0000 0 0 1 1 1 0 0 1 1 1 1 0 1 1
 1110 100 1 1111 1 1 0 0 0 1 1 1 1 1 1 0 1 1
 1111 101 1 1100 1 1 0 0 1 0 0 1 1 1 1 0 1 1